The present invention relates to a chip stack package, and more particularly to a through silicon via chip stack package which facilitates a chip selection.
Packaging technologies for a semiconductor integrated device have been continuously developed to satisfy the demands for mounting efficiency and miniaturization. As the miniaturization and high performance are required in the recent development trends of the electric/electronic appliance, various semiconductor stacking technologies have been developed.
The “stack” referred in a semiconductor industry is a technology in which at least two semiconductor chips or packages are stacked up in a vertical direction. When this stack technology is applied in the field of memory devices, it is possible to realize a packaged product having the memory capacity more than two times the memory capacity of an unpackaged chip, for example, and thus it is possible to increase the efficiency of the mounting area usage.
FIG. 1 is a cross-sectional view illustrating a conventional chip stack package. As shown, chips 110 are stacked on a substrate 120 by the medium of adhesives 130 and each chip 110 is electrically connected to the substrate 120 through a wire 140. An upper surface of the substrate 120 including the stacked chips 110 and the wires 140 is sealed with an encapsulant 150 such as epoxy molding compound (EMC), and a lower surface of the substrate 120 is attached with solder balls 160 as the mounting means to an external circuit.
In FIG. 1, reference numeral 112 denotes a pad, 122 denotes an electrode terminal, 124 denotes a ball land, and 126 denotes a circuit wiring.
However, the conventional chip stack package has several disadvantages in that the operational speed is considered relatively slow due to use of metal wires for signal connections to each chip; the size of the package could not be made more compact since additional area is required on the substrate for a wire bonding; and further the height of the package could not be lowered as the gap for the wire bonding is required on the bonding pads of each chip.
A chip stack package using a through silicon via (hereinafter, referred as TSV) has been proposed for overcoming the above described problems associated with the conventional chip stack packages.
FIG. 2 is a cross-sectional view illustrating a TSV chip stack package. As shown, in the TSV chip stack package 200, a TSV 270 is formed by forming a hole in each chip 210 and filling in the hole with a conductive layer and then an electrical connection between the chips 210 is made by the TSV 270.
In FIG. 2, the reference numeral 212 denotes a pad, 220 denotes a substrate, 222 denotes an electrode terminal, 224 denotes a ball land, 226 denotes a circuit wiring, and 260 denotes a solder ball.
The TSV chip stack package 200 would not require an additional area on the substrate to provide for the electrical connections of wire bonding and would not require presence of a gap between the chips to provide for the wire bonding between the chips and the substrate as shown in FIG. 1. Thus, the TSV chip stack package 200 when compared to the conventional package 100 shown in FIG. 1 is reduces in size and height, because the signal connection lengths between the substrate and chips are shorter, and thereby allowing it possible to increase the operational speed of the chips packaged therein.
In the case of stacking NAND flash memory chips using wire bonding to realize such a chip stack package as shown in FIG. 1, now referring to FIG. 3, a chip selection during the operation of the packaged device can be made possible by making the wire bondings of chips 310a, 310b to a chip selection pad differently from each other such that the electrode terminals 322a, 322b (i.e. Vcc terminal and Vss terminal) are wire bonded to the chips 310a, 310b as shown in FIG. 3.
However, in the case of a TSV chip stack package, selecting a specific chip during the operation of a device is impossible, because no wire bonding as that shown in FIG. 3 is made in a TSV chip stack package. Therefore, the TSV chip stack package requires a novel connection structure for a chip selection.
In addition, in the conventional chip stack package, the chip selection requires increased number of chip selection pads as the number of the stacked chips increases.
However, if the number of chip selection pads are increased, the chip size inevitably increases due to the increased number of pads to be provided in a unit chip, and this prevents optimal miniaturization of the package itself as well as the product utilizing the package.